FIG. 1A is a schematic functional block diagram illustrating a conventional power system. As shown in FIG. 1A, the conventional power system 100 comprises a voltage regulator 110 and a digital circuit 120. The voltage regulator 110 is connected with an external voltage source Vcc. Moreover, the voltage regulator 110 generates an output voltage Vout to a power supply terminal Vcck of the digital circuit 120. When the digital circuit 120 receives the output voltage Vout, the digital circuit 120 is normally operated.
The voltage regulator 110 further has an enabling terminal EN for receiving a power down signal PD from the digital circuit 120. When the power down signal PD is inactivated, the voltage regulator 110 is enabled to issue the output voltage Vout to the digital circuit 120. In case that the power down signal PD is activated, the voltage regulator 110 is disabled, and thus the output voltage Vout is not issued to the digital circuit 120.
When the digital circuit 120 is not operated, the digital circuit 120 activates the power down signal PD. Consequently, the voltage regulator 110 stops issuing the output voltage Vout to the digital circuit 120. After the digital circuit 120 is disabled because the output voltage Vout is not received, the user may switch off the external voltage source Vcc.
For operating the digital circuit 120 again, the user may switch on the external voltage source Vcc. After the external voltage source Vcc is switched on, the voltage regulator 110 is enabled to issue the output voltage Vout to the digital circuit 120. Consequently, the digital circuit 120 can be operated again.
However, after the external voltage source Vcc is switched on, the voltage of the external voltage source Vcc gradually increases from 0V to a stable fixed voltage (e.g., 1.8V). Before the voltage of the external voltage source Vcc reaches the stable fixed voltage, the output voltage Vout from the voltage regulator 110 is unstable. In this situation, the power down signal PD from the digital circuit 120 contains noise. Due to the noise of the power down signal PD, the voltage regulator 110 is disabled and the overall power system 100 is in a deadlock state. When the power system 100 is in the deadlock state, the voltage regulator 110 cannot issue the output voltage Vout. Under this circumstance, the digital circuit 120 cannot be operated.
FIG. 1B is a schematic timing waveform diagram illustrating the signals associated with the digital circuit and the voltage regulator of the conventional power system.
At the time point t0, the external voltage source Vcc is switched on. Consequently, the voltage of the external voltage source Vcc gradually increases from 0V to a stable fixed voltage (e.g., 1.8V).
While the voltage of the external voltage source Vcc gradually increases and does not reach the steady state, the power down signal PD from the digital circuit 120 contains noise at the time point t1. Due to the noise of the power down signal PD, the voltage regulator 110 is disabled.
In other words, the voltage regulator 110 is disabled after the time point t1. Consequently, the output voltage Vout gradually decreases to 0V. Even if the voltage of the external voltage source Vcc reaches the stable fixed voltage at the time point t2, the voltage regulator 110 cannot issue the output voltage Vout. Under this circumstance, the voltage regulator 110 is disabled, and the overall power system 100 is in a deadlock state.